1. Field of the Invention
The present invention relates to a salicide process. More particularly, it relates to a method for using CMP processes in a salicide process to prevent bridging.
2. Description of the Prior Art
Because of the increasing complexity of electronic devices, the dimensions of MOS devices are shrinking, and the source (drain) resistance is increasing to the level of the channel. In order to lower the source (drain) resistance and keep the shallow junction between the metal and MOS intact, the self-aligned silicide process is widely applied in fabricating VLSI under 0.5 .mu.m. Such a process is also called a salicide process.
Titanium is a metal which is capable of reacting with oxygen. Under adequate temperature, titanium easily reacts with silicon to form a compound called TiSi.sub.2 with lower resistance by inter-diffusion. Thus, there is good ohmic contact formed between the interface of titanium and silicon. Presently, titanium is the most popular metal used for the salicide process (Co and Pt are alternatives). FIGS. 1A through 1E illustrate, in cross section, the conventional salicide process.
Referring to FIG. 1A, a basic MOS structure is formed on a semiconductor substrate 10. The MOS structure includes a defined polysilicon gate 14, a thin gate oxide 12, source/drain active regions 16, spacers 20 formed by chemical vapor deposition (CVD), and field oxide 11. After cleaning the wafer in a hydrofluoric acid solution to remove all possible contamination, titanium is sputtered, for example by DC magnetron sputtering, to deposit a titanium layer 30 of a thickness between 200 and 1000 .ANG. over the MOS structure, as shown in FIG. 1B.
Then, the first rapid thermal process, RTP, is performed at between 650 and 800.degree. C. and with a nitrogen gas (N.sub.2) ambient. During the annealing step, titanium reacts with the polysilicon on the gate 14 and the crystalline silicon of the source/drain active regions and forms TiSi.sub.2 (C49 phase) layers 31, however, the titanium on the spacer 20 and the field oxide 11 remain intact, as FIG. 1C illustrates.
Next, selective etching involving two consecutive wet etchings is used to remove the intact titanium layers. The first etching utilizes a mixture of NH.sub.4 OH, H.sub.2 O.sub.2, and H.sub.2 O as the etchant, while the second etching utilizes a mixture of H.sub.2 SO.sub.4 and H.sub.2 O.sub.2 as the etchant. The wet etching dissolves the titanium and titanium nitride layer 30 but does not etch the TiSi.sub.2 layers 31. All the titanium and titanium nitride layers 30 on field oxide 11 and spacer 20 are removed, while the TiSi.sub.2 layers are still left on the polysilicon gate 14 and the source/drain active regions 16, as FIG. 1D illustrates.
Then, the second RTP is performed at about 800-900.degree. C. with a pressure 760 mtorr and with a nitrogen gas (N.sub.2) ambient. During the annealing step, the TiSi.sub.2 layers 31 of C49 phase are transformed to the TiSi.sub.2 layers 32 of C54 phase, as FIG. 1E illustrates. However, the salicide process according to the prior art has the disadvantages described as follows.
In the titanium salicide process, after HF cleaning, titanium is deposited on wafer in a sputter system. During the first RTP, silicon in the poly gate and source/drain area diffuses into titanium layer and reacts with titanium to form C49-TiSi.sub.2. However, if excess silicon diffuses across the spacer region to form silicide (in this example, TiSi.sub.2) on top of the spacer, it cannot be removed by selective etching; consequently, the gate and drain/source area become "bridged" together, resulting in a circuit short. As devices become smaller, the spacer width needs to be reduced correspondingly, and thus the distance between the poly gate and source/drain decreases, thereby increasing the possibility of bridging.
In addition, there is a parasitic capacitor between the polysilicon gate and drain/source, wherein the spacer is one dielectric of the parasitic capacitor. While scaling down the devices, the thickness of the spacer is scaled down too, and the parasitic capacitance is increased, such that the operation rate is slowed down due to the large parasitic capacitance.